Tempe Arizona, US
Phone: xxx-xxx-xxxx
Email: xxx@xxxx.xxx
Looking For: RTL Design Engineer, asic design engineer
Occupation: Architecture and Engineering
Degree: Master's Degree
Career Level: Entry Level
Languages: English/Hindi/Telugu
Highlights:I have completed my Masters at Arizona State University in Electrical Engineering
Skills:Verilog, System Verilog
Goal:To contribute to the evolving innovations in semiconductor industry mainly in digital design
Arizona State University 08/2022 - 05/2024
Tempe, Arizona, United States
Degree: Master's Degree
Major:Electrical Engineering
Electrical Engineering graduate student seeking full-time opportunities in ASIC/RTL CPU Design, Design Verification and Memory technologies in 2024. Demonstrated proficiency in hardware design, verification, and synthesis, with a keen interest in contributing to innovative projects in these domains
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, US