Highlights:I gained my Master's degree in Computer Engineering at Arizona State University, I hold specialization in VLSI field. I have performed internship with Trilinear Technologies as an RTL Design Engineer. My prior experience as an Research Assistant at Secure ,Trusted and Assured Microelectronics Center (STAM) at ASU has helped me gain experience over several aspects and tools required for a ASIC / Physical Design role. I am open to full time opportunities and look forward to collaborate with enthusiastic and problem solving Engineers to work towards figuring out the intricacies of any problem and achieving a solution

Skills:

Goal:I am looking for opportunities in the VLSI field and am will currently start on the F1 OPT Visa on Feb 5,2023

Certification:I have certifications in 1. VLSI - Physical Design Flow 2. Clock Tree Synthesis 3. Static Timing Analysis

Honor:Received a New American University Scholarship valued at $10,000.00 from Arizona State University based on my academic performance. Received a scholarship of Rs.50,000 in Bachelors for being top performer consistently during my stint in college.

IC Design Engineer 05/2023 - 12/2023
Trilinear Technologies, Portland, Oregon United States
? Developed RTL for code color space conversion module and unit level testbench by performing simulation successfully. ? Responsible for collecting the Linting, CDC reports and performed the regression tests for the IP cores for RTL verification. ? Performed Code and Functional coverage and achieved 95% coverage for the Anisotropic video Scaler Core. ? Worked on automating the process for the IPXACT files and thereby reducing the need for the manual effort.
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Research Assistant 01/2023 - 05/2023
Arizona State University, Tempe, Arizona United States
? Developed the ASIC Design of Havasu Processor with Physical Design team starting from RTL to GDSII. ? Worked extensively on the automatic placement of the SRAM Memory blocks using a python script minimizing efforts. ? Developed floor plan for the chip level including power planning, placement, CTS and Routing. ? Decreased the congestion by handling the QoR reports post PNR and by fixing the setup and hold violations.
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Sathyabama Institute of Science and Technology 07/2015 - 07/2019
Chennai, Tamilnadu, India
Degree: Bachelor's Degree
Major:Electronics and Communication Enineering
Bachelors degree with a GPA of 9.46/10.00 in Electronics and Communications Engineering

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