Highlights:

Skills:UVM-SV, Constrained Random Verification, C Driven, ASIC Verification, VHDL, Verilog, and SystemVerilog, Python, C, C++, Shell, Makefile, TCL, AXI,APB, AHB, VCS, Verdi, IC Compiler, Linux, SVN, Git, Jira, Jama

Senior ASIC Verification Engineer 06/2024 - current
Sondrel Ltd, Rabat, Morocco
Industry: Semiconductor and ASIC Design
? C Tests Development: Created C-based test cases to validate system-level functionality using DPI-C functions. ? Tests Promotion: Promoted successful IP-level tests to top-level, ensuring full system interaction and integration. ? Fault and Connectivity Checks: Developed connectivity tests and debugged failing functional tests in regression to achieve 100% verification plan coverage.
--
Junior ASIC Verification Engineer 08/2022 - 06/2024
Sondrel Ltd, Rabat, Morocco
Full verification of a Clock Generation IP for a Radar On Chip Project.
IP Verification- Clock Generation IP for Automotive Radar-on-Chip ? Verification Plan (HVP): Created a detailed high-level verification plan, outlining verification strategies, test scenarios, and coverage goals to ensure the IP met all functional requirements. ? UVMTestbench Building: Designed and implemented a reusable, scalable UVM testbench architecture to verify the clock generation IP. ? Random Constrained Verification: Developed and executed randomized, constrained-random verification environments, fine-tuning constraints to hit corner cases and ensure thorough functional validation. ? Creating Test Cases: Developed random and directed test cases to verify various modes of operation, registers access, and timing behaviors of the clockgen IP. ? Functional / Code Coverage: Tracked and improved functional and code coverage, ensuring 100% functionality and corner cases coverage. ? Assertion Implementation: Integrated SystemVerilog assertions (SVA) to verify AXI4-Lite protocol compliance, timing constraints, and corner-case scenarios during simulation. ? Regressions Management: Automated and managed regression tests with Jenkins to ensure consistent verification and catch any regressions in design as the project evolved. ? RTL Debugging: Identified, analyzed, and debugged bugs in the ClockGen IP RTL code, collaborating with the design team to resolve issues and validate fixes.--

Login to view resume: ASIC Verifiation Engineer - UVM-SV, Constrained Random Verification, C Driven Verification,VHDL, Verilog,SystemVerilog,Python,C, C++, Shell, Makefile, TCL,AMBA (APB, AHB and AXI), SPI, I2C, UART,VCS, Verdi, IC Compiler,Modelsim, Questasim,Linux,SVN, Git,Jira, Jama